Technology Mapping for Robust Asynchronous Threshold Networks

As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge in synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, there is currently little CAD support for such robust methodologies. In this paper, an algorithm for technology mapping of robust asynchronous threshold networks is presented. The proposed algorithm is the first to systematically optimize for either delay or area, without destroying the hazard-freedom properties of the initial unoptimized circuits. The algorithm was implemented and experiments were performed on a near-complete industrial DES circuit provided by Theseus Logic, using a particular asynchronous threshold circuit style called NCL (Null Convention Logic), which had been already optimized in an existing constrained asynchronous synthesis flow based on synchronous CAD tools. Average delay improvements up to 26.7% and area improvements up to 4.5% were obtained, when considering the largest subcircuits (with over 400 inputs and outputs). When only the single longest path delay of each subcircuit is considered, the algorithm obtained worst-case delay improvements up to 26.4%. Though the proposed method is applied in the NCL design flow, the contribution is general enough to be used for other robust asynchronous threshold